1. Field of the Invention
The present invention relates to band-gap reference voltage source circuits which serve as reference voltage sources in semiconductor integrated circuits.
The present application claims priority on Japanese Patent Application No. 2008-14961, the content of which is incorporated herein by reference.
2. Description of Related Art
Various technologies regarding band-gap reference voltage source circuits have been developed and disclosed in various documents such as Patent Documents 1 to 3.    Patent Document 1: Japanese Unexamined Patent Application Publication No. H10-232724    Patent Document 2: Japanese Unexamined Patent Application Publication No. H10-143265    Patent Document 3: Japanese Unexamined Patent Application Publication No. 2007-249948
The constitution and operation of a band-gap reference voltage source circuit will be described with reference to FIGS. 5 to 11.
The band-gap reference voltage source circuit of FIG. 5 is constituted of a differential amplifier AMP 1 and a diode-pair circuit BRG_Diode_Pair, which are illustrated as blocks defined by dotted lines. In the diode-pair circuit BRG_Diode_Pair, load resistors R1 and R2 are connected to diodes D1 and D2 having different junction areas, wherein a resistor R3 is further connected to the diode D2 having a larger junction area. A node IN1 formed between the diode D1 and the resistor R1 serves as one input terminal of the differential amplifier AMP1, while a node IN2 formed between the resistors R2 and R3 serves as another input terminal of the differential amplifier AMP1. The output terminal of the differential amplifier AMP1 is connected to an output terminal BG_REF which is also connected with the resistors R1 and R2. When the differential amplifier AMP1 has an adequately high amplification factor of voltage, the differential amplifier AMP1 operates to make a differential voltage ΔVIN=V_VIN2−V_IN1 become zero, wherein V_IN1 designates a potential at the node IN1, and V_IN2 designates a potential at the node IN2. Currents I1 and I2 flowing through the diodes D1 and D2 are expressed by equations (1) and (2).
                              I          ⁢                                          ⁢          1                =                                            V_BG              ⁢              _REF                        -                          V_IN              ⁢                                                          ⁢              1                                            R            ⁢                                                  ⁢            1                                              (        1        )                                          I          ⁢                                          ⁢          2                =                                            V_BG              ⁢              _REF                        -                          V_IN              ⁢                                                          ⁢              2                                            R            ⁢                                                  ⁢            2                                              (        2        )            
In equations (1) and (2), V_BG_REF designates a reference voltage at the reference voltage output terminal BG_REF, and R1 and R2 designates the resistances of the resistors R1 and R2. For the sake of convenience, the following description is made based on the presumption of R1=R2. In this case, the same potential is set to the nodes IN1 and IN2, hence, I1=I2.
The differential amplifier AMP1 is constituted of P-channel MOS (Metal Oxide Semiconductor) transistors MP1, MP3, and MP4 whose sources are connected to a drive voltage (electronic power-supply voltage) VDD, an N-channel MOS transistor MN3 whose source is connected to a ground potential VSS, an N-channel MOS transistor MN1 whose drain is connected to the drain of the transistor MP3 and whose source is connected to the drain of the transistor MN3, an N-channel MOS transistor MN2 whose drain is connected to the drain of the transistor MP4 and whose source is connected to the drain of the transistor MN3, and a phase compensation capacitor C1. The gates of the transistors MP3 and MP4 are connected together and are also connected to the drain of the transistor MP4. The gate of the transistor MP1 is connected to the drain of the transistor MP3, and the capacitor C1 is connected between the gate and source of the transistor MP1. The gate of the transistor MN3 receives an output voltage V_BIAS_N of a bias generator which is configured of a current mirror circuit (not shown), thus controlling the drain current (or tail current) I0 at a constant value.
In the differential amplifier AMP1, the N-channel MOS transistors MN1, MN2, and MN3, and the P-channel transistors MP3 and MP4 form a differential amplification block whose input terminals correspond to the gates of the transistors MN1 and MN2 and whose output terminal corresponds to the drain of the transistor MP1.
When the junction area of the diode D1 is N times (where N>1) larger than the junction area of the diode D1, the relationships defined by equations (3) and (4) are established between forward voltages VD1 and VD2 of the diodes D1 and D2.
                              I          ⁢                                          ⁢          1                =                  J          ⁢                                          ⁢                      0            ·            A                    ⁢                                          ⁢                      1            ·                          exp              ⁡                              [                                                      VD                    ⁢                                                                                  ⁢                    1                                                        (                                          kT                      /                      q                                        )                                                  ]                                                                        (        3        )                                          I          ⁢                                          ⁢          2                =                  J          ⁢                                          ⁢                      0            ·            A                    ⁢                                          ⁢                      2            ·                          [                                                VD                  ⁢                                                                          ⁢                  2                                                  (                                      kT                    /                    q                                    )                                            ]                                                          (        4        )            
In equations (3) and (4), J0 designates a reverse saturation current per unit area; A1 and A2 designate the junction areas of the diodes D1 and D2; k designates a Boltzmann constant; and q designates an electron charge.
The following equations (5) and (6) are produced based on equations (3) and (4).
                                          I            ⁢                                                  ⁢            1                                I            ⁢                                                  ⁢            2                          =                                            (                                                A                  ⁢                                                                          ⁢                  1                                                  A                  ⁢                                                                          ⁢                  2                                            )                        ·                          exp              ⁡                              [                                                      Δ                    ⁢                                                                                  ⁢                    VD                                                        (                                          kT                      /                      q                                        )                                                  ]                                              =          1                                    (        5        )                                          Δ          ⁢                                          ⁢          VD                =                                            VD              ⁢                                                          ⁢              1                        -                          VD              ⁢                                                          ⁢              2                                =                                                    (                                  kT                  q                                )                            ·                              ln                ⁡                                  (                                                            A                      ⁢                                                                                          ⁢                      2                                                              A                      ⁢                                                                                          ⁢                      1                                                        )                                                      =                                          (                                  kT                  q                                )                            ·                              ln                ⁡                                  (                  N                  )                                                                                        (        6        )            
Equation (7) is produced based on equations (5) and (6) in which ΔVD designates a voltage applied to the resistor R3.
                              I          ⁢                                          ⁢          1                =                              I            ⁢                                                  ⁢            2                    =                                    (                              kT                q                            )                        ·                                          ln                ⁡                                  (                  N                  )                                                            R                ⁢                                                                  ⁢                3                                                                        (        7        )            
In equation (7), R3 designates the resistance of the resistor R3. Based on the above equations, the reference voltage V_BG_REF is expressed by equation (8).
                              V_BG          ⁢          _REF                =                              VD            ⁢                                                  ⁢            1                    +                                    (                                                R                  ⁢                                                                          ⁢                  1                                                  R                  ⁢                                                                          ⁢                  3                                            )                        ·                          (                              kT                q                            )                        ·                          ln              ⁡                              (                N                )                                                                        (        8        )            
In equation (8), the first term “VD1” has a negative coefficient of temperature dependency, while the second term has a positive coefficient of temperature dependency. By performing differentiation with respect to temperature T (which is then set to zero), it is possible to calculate the condition for canceling the temperature dependency, details of which are omitted, but which is canceled when the output voltage is approximately set to a band-gap Eg (ranging from 1.1 V to 1.2 V).
Based on the presumption where V_BG_REF=1.2 V, VD1=0.6 V, N=8, T=300 K, and R1=R2, equation (8) is developed into equation (9).
                              1.2          ⁢                                          ⁢          V                =                              0.6            ⁢                                                  ⁢            V                    +                                                    (                                                      R                    ⁢                                                                                  ⁢                    1                                                        R                    ⁢                                                                                  ⁢                    3                                                  )                            ·              0.0538                        ⁢                                                  ⁢            V                                              (        9        )            
Thus, R1/R3=11.15 is calculated. At this time, the band-gap reference voltage source circuit of FIG. 5 is designed in the condition of I1=1 μA, thus producing equation (10).
                              R          ⁢                                          ⁢          3                =                                            0.0538              ⁢                                                          ⁢              V                                      1              ⁢                                                          ⁢              µ              ⁢                                                          ⁢              A                                =                      53.8            ⁢                                                  ⁢            k            ⁢                                                  ⁢            Ω                                              (        10        )                                          R          ⁢                                          ⁢          1                =                              11.15            ⁢            R            ⁢                                                  ⁢            3                    =                      600            ⁢                                                  ⁢            k            ⁢                                                  ⁢            Ω                                                          
The above calculations are created based on the steady-state condition of the band-gap reference voltage source circuit in which the operation is started normally. In the electronic power-supply activation (power-on event), the differential amplifier AMP1 is set to a transient state in which the same potential is not necessarily set to the nodes IN1 and IN2. The following examination will be given with respect to the state of the diode-pair block BGR_Diode_Pair in the band-gap reference voltage source circuit whose reference voltage V_BG_REF is not set to a desired level.
The reference voltage V_BG_REF is given in conjunction with an arbitrary value of the current I1 by equation (11)V—BG_REF=VD1+R1·I1  (11)
Since the slope of logarithmic current-voltage characteristics of a diode is calculated as (kT/q)ln10=60 mV/decade using T=300K, the forward voltage VD1 of the diode D1 can be expressed by equation (12).
                              VD          ⁢                                          ⁢          1                =                              0.6            ⁢                                                  ⁢            V                    +                      0.06            ⁢                                                  ⁢                          V              ·                              log                (                                                      I                    ⁢                                                                                  ⁢                    1                                                        1                    ⁢                                                                                  ⁢                    µ                    ⁢                                                                                  ⁢                    A                                                  )                                                                        (        12        )            
Thus, equation (11) is developed into equation (13).
                              V_BG          ⁢          _REF                =                              0.6            ⁢                                                  ⁢            V                    +                      0.06            ⁢                                                  ⁢                          V              ·                              log                (                                                      I                    ⁢                                                                                  ⁢                    1                                                        1                    ⁢                                                                                  ⁢                    µ                    ⁢                                                                                  ⁢                    A                                                  )                                              +                      R            ⁢                                                  ⁢                          1              ·              I                        ⁢                                                  ⁢            1                                              (        13        )            
Similarly, the reference voltage V_BG_REF is given in conjunction with an arbitrary value of the current I2 by equation (14).V—BG_REF=VD2+(R2+R3)·I2  (14)
Since the junction area of the diode D2 having the voltage VD2 is N (where N=8) times larger than the junction area of the diode D1 having the voltage VD1, the voltage VD1 is expressed by equation (15).
                              V          ⁢                                          ⁢          D          ⁢                                          ⁢          2                =                              0.6            ⁢            V                    +                      0.06            ⁢                          V              ·                              log                ⁡                                  (                                                            I                      ⁢                                                                                          ⁢                      2                                                                                      N                        ·                        1                                            ⁢                                                                                          ⁢                      μ                      ⁢                                                                                          ⁢                      A                                                        )                                                                                        (        15        )            
Thus, equation (14) is developed into equation (16).
                              V_BG          ⁢          _REF                =                              0.6            ⁢            V                    +                      0.06            ⁢                          V              ·                              log                ⁡                                  (                                                            I                      ⁢                                                                                          ⁢                      1                                                              N                      ⁣                                                                        ·                          1                                                ⁢                        μ                        ⁢                                                                                                  ⁢                        A                                                                              )                                                              +                                                    (                                                      R                    ⁢                                                                                  ⁢                    2                                    +                                      R                    ⁢                                                                                  ⁢                    3                                                  )                            ·              I                        ⁢                                                  ⁢            2                                              (        16        )            
Since both the equations (13) and (16) indicate the same reference voltage V_BG_REF at the reference voltage output terminal BG_REF, it is possible to produce equation (17).
                                          0.06            ⁢                                                  ⁢                          V              ·                              log                ⁡                                  (                                      N                    ·                                                                  I                        ⁢                                                                                                  ⁢                        1                                                                    I                        ⁢                                                                                                  ⁢                        2                                                                              )                                                              +                      R            ⁢                                                  ⁢                          1              ·              I                        ⁢                                                  ⁢            1                    -                                                    (                                                      R                    ⁢                                                                                  ⁢                    2                                    +                                      R                    ⁢                                                                                  ⁢                    3                                                  )                            ·              I                        ⁢                                                  ⁢            2                          =        0                            (        17        )            
Equation (17) can be further developed into equation (18) by use of the relationship of 0.06V=(kT/q)ln10.
                                                        (                              kT                q                            )                        ·                          ln              ⁡                              (                                  N                  ·                                                            I                      ⁢                                                                                          ⁢                      1                                                              I                      ⁢                                                                                          ⁢                      2                                                                      )                                              +                      R            ⁢                                                  ⁢                          1              ·              I                        ⁢                                                  ⁢            1                    -                                                    (                                                      R                    ⁢                                                                                  ⁢                    2                                    +                                      R                    ⁢                                                                                  ⁢                    3                                                  )                            ·              I                        ⁢                                                  ⁢            2                          =        0                            (        18        )            
It is possible to calculate the current I2 based on equations (17) and (18) if the value of the current I1 is given. The results of calculations regarding the currents I1 and I2 and the reference voltage V_BG_REF of the reference voltage output terminal BG_REF are shown in FIGS. 6, 7, and 8.
FIG. 6 shows the relationship between the reference voltage V_BG_REF and the sum of the currents I1 and I2 flowing through the diodes D1 and D2, i.e. I1+I2, in the band-gap reference voltage source circuit. FIG. 6 clearly shows that the currents I1 and I2 may rapidly decrease below V_BG_REF=0.5 V.
FIG. 7 shows the relationship between the reference voltage V_BG_REF and the potentials V_N1 and V_IN2 at the terminals IN1 and IN2 in the band-gap reference voltage source circuit. FIG. 7 clearly shows that the potential difference between the terminals IN1 and IN2 may rapidly decrease below V_BG_REF=0.5 V.
FIG. 8 shows the relationship between the reference voltage V_BG_REF and the differential voltage ΔVIN=V_IN2−V_IN1 (between the terminals IN1 and IN2) in the band-gap reference voltage source circuit. FIG. 8 clearly shows that the differential voltage ΔVIN may rapidly be asymptotic in zero below V_BG_REF=0.5 V.
In the initial stage of the electronic power-supply activation (power-on event) in which the power-supply voltage is so low that no current flows in the diode-pair block BGR_Diode_Pair in the band-gap reference voltage source circuit, and both the potentials V_IN1 and V_IN2 are very low such as approximately 0.4 V. In order to allow the tail current I0 to flow in the differential amplifier AMP1, it is necessary to establish a first condition in which the gate-source voltage of the transistor MN1 is higher than a threshold voltage VT(MN1) of the transistor MN1 and a second condition in which the drain-source voltage VDS(MN3) of the transistor MN3 serving as a constant current source is at least 3 kT/q. That is, the differential amplifier AMP1 does not operate without the relationship of inequality (19).
                              V_IN          ⁢                                          ⁢          1                ≥                              V            ⁢                                                  ⁢                          T              ⁡                              (                                  M                  ⁢                                                                          ⁢                  N                  ⁢                                                                          ⁢                  1                                )                                              +                                    3              ⁢                                                          ⁢              kT                        q                                              (        19        )            
In the above inequality (19), the voltage VT(MN1) is not strictly the threshold voltage of MN1. Usually, a threshold voltage is defined as a gate-source voltage allowing a predetermined current to flow in a MOS transistor. A typical value of the predetermined current is 0.1 μA per unit gate width, i.e. Ivt=0.1 μA/μm. If the gate width of MN1 is W=10 μm, VT(MN1) causes 1 μA of drain current. However, in actuality, the differential amplifier AMP1 is capable of operating with a lower current than 1 μA. By use of a tail current Ioc (representing the operation limit of the differential amplifier AMP1) and a coefficient S representing the slope of logarithmic characteristics between the drain current and gate voltage in a tailing region, inequality (19) can be developed into inequality (20).
                              V_IN          ⁢                                          ⁢          1                ≥                              V            ⁢                                                  ⁢                          T              ⁡                              (                                  M                  ⁢                                                                          ⁢                  N                  ⁢                                                                          ⁢                  1                                )                                              +                      S            ·                          log              ⁡                              (                                  Ioc                                      W                    ·                    Ivt                                                  )                                              +                                    3              ⁢                                                          ⁢              kT                        q                                              (        20        )            
In numerical conditions where VT(MN1)=0.55 V, S=90 mV/decade, Ioc=10 nA, W=10 μm, Ivt=0.1 μA/μm, and T=300 K, inequality (20) can be developed as V_IN1≧0.55V−0.18V+0.078V=0.448V.
The above numerals and FIGS. 7 and 8 show that inequality (19) is not established when no current flows through the diodes D1 and D2 of the diode-pair block BGR_Diode_Pair in the initial stage of electronic power-supply activation (power-on event) of the band-gap reference voltage source circuit, wherein the tail current I0 does not flow in the differential amplifier AMP1, which does not operate at high probability. In other words, since the input voltages of AMP1, V_IN1 and V_IN2 are very low such as approximately 0.4 V, the differential amplifier AMP1 cannot operate so that the transistor MP1 is still turned off, wherein there is no means for boosting the potentials V_IN1 and V_IN2. That is, the band-gap reference voltage source circuit is in a zero-current state and cannot move into an operation state.
To avoid such a zero-current state in which the band-gap reference voltage source circuit cannot start operation, it is possible to provide a countermeasure in which a current is forced to flow into a desired point of the band-gap reference voltage source circuit during a transient period of boosting the drive voltage (electronic power-supply voltage) VDD which is detected. FIG. 9 shows an example of the countermeasure adapted to the band-gap reference voltage source circuit of FIG. 5.
The circuitry of FIG. 9 includes a detector block VDD_Detector in addition to the circuitry of the band-gap reference voltage source circuit shown in FIG. 5, wherein parts identical to those shown in FIG. 5 are designated by the same reference numerals; hence, duplicate descriptions thereof are simplified or omitted. The detector block VDD_Detector is designed such that the gate of an N-channel MOS transistor MN14 is connected to a node N1 between resistors R9 and R10 which are connected between the drive voltage (electronic power-supply voltage) VDD and the ground potential VSS; a resistor R11 is connected between the drive voltage (electronic power-supply voltage) VDD and a node N2 (corresponding to the drain of the transistor MN14; an inverter whose input terminal corresponds to the node N2 is configured of a P-channel MOS transistor MP12 and an N-channel MOS transistor MN15; an inverter whose input terminal corresponds to a node N3 (which serves as an output terminal of the inverter configured of the transistors MP12 and MN15) is configured of a P-channel MOS transistor MP13 and an N-channel MOS transistor MN16; an inverter whose input terminal corresponds to a node N4 (which servers as an output terminal of the inverter configured of the transistors MP13 and MN16) is configured of a P-channel MOS transistor MP14 and an N-channel MOS transistor MN17; and the gate of a P-channel MOS transistor MP15 is connected to a node N5 (which serves as an output terminal of the inverter configured of the transistors MP14 and MN17).
In the detector block VDD_Detector, a fragmental voltage divided by a voltage divider configured of the resistors R9 and R10 is applied to the gate of the transistor MN14. The current flowing through the transistor MN14 increases as the drive voltage (electronic power-supply voltage) VDD increases, whereby when a resistive voltage drop of the resistor R11 becomes sufficiently high, the output signal of the inverter configured of the transistors MP12 and MN15 is inverted from a low level to a high level. Then, the level of the node N5 turns to a high level from a low level as same as the level of the node N3; hence, the gate potential of the transistor MP15 is changed from a low level to a high level. That is, when the drive voltage (electronic power-supply voltage) VDD is relatively low, the transistor MP15 is turned on so as to force a current to flow into the output terminal BG_REF. As the drive voltage (electronic power-supply voltage) VDD becomes higher, the transistor MP15 is turned off so that the circuitry of FIG. 9 operates similar to the band-gap reference voltage source circuit of FIG. 5. The detector block VDD_Detector detects the lowness of the drive voltage (electronic power-supply voltage) VDD so as to turn on the transistor MP15, thus avoiding the zero-current state in which the band-gap reference voltage source circuit cannot start operation.
In the detector block VDD_Detector shown in FIG. 9, a transient voltage Vtrip, which may correspond to a fragmentation of the drive voltage (electronic power-supply voltage) VDD occurring when the state of the transistor MN14 is changed from Off to ON, may presumably depend upon the threshold voltage VT(MN14) of the transistor MN14 when the resistor R11 has a relatively high resistance. By use of a voltage-division ratio α=R10/(R9+R10) of the resistive voltage divider configured of the resistors R9 and R10, the transient voltage Vtrip is given by equation (21).
                    Vtrip        =                              V            ⁢                                                  ⁢                          T              ⁡                              (                                  M                  ⁢                                                                          ⁢                  N                  ⁢                                                                          ⁢                  14                                )                                              α                                    (        21        )            
A transient time Tt is calculated by equation (22) using a steady-state voltage VDD0 of the drive voltage (electronic power-supply voltage) VDD, and a rising time Tr which is a transient time from 0V to VDD0 of the drive voltage (electronic power-supply voltage) VDD.
                    Tt        =                  Tr          ·                                    V              ⁢                                                          ⁢                              T                ⁡                                  (                                      M                    ⁢                                                                                  ⁢                    N                    ⁢                                                                                  ⁢                    14                                    )                                                                                    α                ·                V                            ⁢                                                          ⁢              D              ⁢                                                          ⁢              D              ⁢                                                          ⁢              0                                                          (        22        )            
To turn on the pull-up transistor MP15, the drive voltage (electronic power-supply voltage) VDD should be higher than the absolute value of the threshold voltage of the transistor MP15, i.e. |VT(MP15)|. The potential of the output terminal BG_REF is maintained at VDD for a time Th which is given by equation (23).
                    Th        =                  Tr          ·                                    [                                                                    V                    ⁢                                                                                  ⁢                                          T                      ⁡                                              (                                                  M                          ⁢                                                                                                          ⁢                          N                          ⁢                                                                                                          ⁢                          14                                                )                                                                              α                                -                                                                        V                    ⁢                                                                                  ⁢                                          T                      ⁡                                              (                                                  M                          ⁢                                                                                                          ⁢                          P                          ⁢                                                                                                          ⁢                          15                                                )                                                                                                                          ]                                      V              ⁢                                                          ⁢              D              ⁢                                                          ⁢              D              ⁢                                                          ⁢              0                                                          (        23        )            
Equation (23) shows that the time Th for maintaining the potential of the output terminal BG_REF at VDD is proportional to the rise time of the drive voltage (electronic power-supply voltage) VDD. FIG. 10 diagrammatically shows the above relationships, wherein the horizontal axis represents time, and the vertical axis represents voltage of the VDD_Detector output. FIG. 10 shows the time-related variations of the potential of the output terminal BG_REF after “zero” time at which the drive voltage (electronic power-supply voltage) starts rising, wherein dotted lines indicate the level of the drive voltage (electronic power-supply voltage) VDD, and solid lines indicate the potential of the output terminal BG_REF.
When the time Th defined by equation (23) is longer than a start-up time required for the differential amplifier AMP1 to start the operation, it is possible to reliably start the operation of the band-gap reference voltage source circuit. Next, the start-up time of the differential amplifier AMP1 will be examined in detail.
It is presumed that the differential amplifier AMP1 of the band-gap reference voltage source circuit of FIG. 9 starts operation when the transistor MP1 is turned on to allow a current to flow therethrough. Hence, a time which is required to decrease the voltage of the node A1_OUTB by a threshold voltage VT(MP1) of the transistor MP1 from its initial voltage of VDD level is regarded as the minimum (or worst) start-up time of AMP1.
By use of a coefficient S representing the slope of the drain current (in logarithm) and gate-source voltage, a mutual conductance gm applied to a pair of the transistors MN1 and MN2 in the differential amplifier AMP1 is given by equation (24).
                    gm        =                              (                                          I                0                            /              2                        )                                (                                          S                /                ln                            ⁢                                                          ⁢              10                        )                                              (        24        )            
In equation (24), I0 designates a tail current of the differential amplifier AMP1, wherein both the transistors MN1 and MN2 operate in a sub-threshold region. A load capacitance CL is given by equation (25) using gate capacitances Cmn1, Cmp3, and Cmp1 of the transistors MN1, MP3, and MP1.CL=Cmn1+Cmp3+(AV+1)·(Cmp1+C1)  (25)
In equation (25), ΔV designates a voltage amplification factor of the transistor MP1 whose source is grounded, wherein the term (ΔV+1) designates a coefficient of a mirror effect. This description is given with respect to the time required for the transistor MP1 to be turned on; hence, ΔV=0.
Since a half of the differential voltage ΔVIN representing the differential input amplitude applied to a pair of the transistors MN1 and MN2 is applied to the transistor MN1 as its input amplitude, a time Tamp for reducing the potential of the gate A1_OUTB of the transistor MP1 by the threshold voltage VT(MP1) is given by equation (26).
                    Tamp        =                  C          ⁢                                          ⁢                      L            ·                                          V                ⁢                                                                  ⁢                                  T                  ⁡                                      (                                          MP                      ⁢                                                                                          ⁢                      1                                        )                                                                              gm                ·                                                      Δ                    ⁢                                                                                  ⁢                    V                    ⁢                                                                                  ⁢                    I                    ⁢                                                                                  ⁢                    N                                    2                                                                                        (        26        )            
By use of prescribed values such as I0=1 μA, S=100 mV/decade, CL=1 pF, VT(MP1)=−0.55 V, and ΔVIN=−10 mV, equation (26) produces the result of Tamp=9.55 μs.
By use of prescribed values such as α=0.5, VT(MN14)=0.55 V, VT(MP15)=−0.55 V, and VDD0=1.8 V, equation (23) produces the result of Th=0.3056·Tr; hence, Tr>31 μs when Th>Tamp. That is, the drive voltage (electronic power-supply voltage) VDD whose rise time in waveform is shorter than 31 μs may have a high risk of causing an operational failure in which the band-gap reference voltage source circuit of FIG. 9 fails to start operation.
As described above, the present inventor has recognized that substantially no current flows in the band-gap reference voltage source circuit of FIG. 5 in the rise time of the drive voltage (electronic power-supply voltage) VDD, thus causing a zero-current state in which the band-gap reference voltage source circuit cannot start operation. In order to avoid the occurrence of the zero-current state, the band-gap reference voltage source circuit of FIG. 9 introduces the detector block VDD_Detector to detect the rising of the drive voltage (electronic power-supply voltage) VDD so as to force a current to flow; however, there still remains a condition which does not prevent the zero-current state. This condition may cause negative influences to band-gap reference voltage source circuits in consideration of variations of manufacturing processes and variations of characteristics of transistors.
FIG. 11 shows simulation results of the band-gap reference voltage source circuit of FIG. 9, wherein the horizontal axis represents time while the vertical axis represents voltage.
Specifically, FIG. 11 shows three waveforms designated by numerals 1, 2, and 3, wherein the waveform 1 (drawn with dotted line and curve) indicates the drive voltage (electronic power-supply voltage) VDD, the waveform 2 (drawn with dashed line and curve) indicates the signal of the output terminal BG_REF which is simulated without consideration of variations of thresholds of transistors, and the waveform 3 (drawn with solid line and curve) indicates the signal of the output terminal BG_REF which is simulated with consideration of variations of thresholds of transistors. The level of the waveform 2 increases up to a prescribed voltage with respect to time, while the waveform 3 suffers from a short pullup time and does not substantially increase in level.
The band-gap reference voltage source circuit, in which the detector block detects the rising of the drive voltage (electronic power-supply voltage) VDD so as to achieve pullup to VDD, suffers from unstable variations of potentials and pullup times due to various parameters such as variations of the rise time of the drive voltage (electronic power-supply voltage), variations of processes, variations of transistors, and variations of temperature; hence, it is very difficult to secure a substantial potential for a sufficient time for starting the operation of the differential amplifier AMP1. For this reason, a starting circuit for securing a substantial potential for a sufficient time for starting the operation of the differential amplifier AMP1 is necessary for every LSI circuitry using the band-gap reference voltage source circuit to prevent a hangup failure occurring in electronic power-supply activation (power-on event).